1. Field of the Invention
This application relates generally to fabricating integrated circuits, and more particularly to a process for forming an epitaxial channel vertical floating gate transistor.
2. Description of the Related Art
Conventional thin film processing techniques are now commonly used to produce integrated circuits. These integrated circuits may incorporate various devices, including transistors. One type of transistor is a floating gate transistor, which is often used in non-volatile memories because the floating gate can hold charge, and thus retain stored information, without requiring a connection to a power supply.
As with a standard transistor, the floating gate transistor uses a control gate that is insulated from a channel in which conduction between the transistor source and drain may occur dependent upon the gate to source voltage. Specifically, appropriate biasing of the control gate can create an electrical field that attracts charge carriers into the channel to provide a conductive path between the source and drain of the floating gate transistor. However, unlike the standard transistor, the floating gate transistor includes a floating gate that is typically located between the control gate and the channel region. The floating gate transistor can be programmed or erased by causing charge carriers to enter or leave the floating gate, which can retain the charge carriers because it is electrically isolated. The presence or absence of charge carriers on the floating gate dictates the threshold voltage of the floating gate transistor; this is used to identify the information stored in the floating gate transistor.
As with the standard transistor, increasing scales of integration mandate the inclusion of increasing numbers of floating gate transistors on a single chip, which spawns the demand for closer spacing in order to allow their inclusion in a finite amount of space. An important dimension in the fabrication of semiconductor devices, including floating gate transistors, is the length of the channel. The length of the channel affects transistor operation, and impacts the number of transistors that can be provided in a given space. It is therefore desirable to minimize the channel size and to provide consistent channel dimensions and characteristics when fabricating integrated circuits.
Other concerns in the fabrication of integrated circuits are the provision of source and drain regions that do not have high resistivity, particularly for low voltage applications, where high resistivity prevents proper operation. Also, it is desirable to retain control of the resistivity of the source and drain regions during fabrication, so that produced transistors can have substantially equal source and drain resistivity, facilitating symmetrical read operations for the floating gate transistor (i.e., interchangeable source and drain regions).
A vertical floating gate transistor includes a drain (or source) region that has a greater depth within the substrate than does its source (or drain) region, as well as an intervening channel. The source, drain and channel are generally arranged in a vertical direction. This arrangement can be advantageous because it consumes less substrate surface area than horizontal arrangements. Also, the vertical transistor can provide a transistor having a channel length that is smaller than that which could be produced for the horizontal type, which is more directly limited by the minimum photolithographic resolution. Thus, it may be more desirable to implement vertical transistors for increasing scales of integration.
Certain aspects of conventional vertical transistors, however, remain problematic. For example, the barriers to controlling the resistivity of the lower doped region makes it difficult to produce a device having symmetry. Additionally, producing floating gate transistors with accurate, small channel lengths is desired. Finally, since the floating gate transistor is often used in memories where low power operation is desired, it is imperative to provide a deeper doped region with a low resistivity.
Thus, there remains a need for a vertical floating gate transistor with a minimized, consistent channel length, and which has upper and lower source/drain regions with low resistivity, and which offers symmetrical read operations.